For a semiconductor substrate, high surface flatness is required because semiconductor devices are formed on a main surface thereof. This is because the minimum line width of wires constituting the semiconductor devices is very small, 0.2 μm or less, and therefore failures such as breaking are required to be reduced by flattening a main surface of the semiconductor substrate. This minimum line width of wires tends to be even smaller for increasing integration degree of semiconductor devices. Along with this, more improvement of surface flatness of semiconductor substrates has been required.
For improving the surface flatness of semiconductor substrates, polishing materials for polishing the surface become important. In the case of single-side polishing such as CMP (Chemical Mechanical Polishing), as shown in FIG. 3, a semiconductor substrate 11 held by a polishing head 10 is pressed with a desired pressure onto a polishing pad 13 attached on a polishing apparatus turn table 12. The turn table 12 and the semiconductor substrate 11 rotate by a predetermined rotation rate, and at the same time, a polishing agent (slurry) 15 is supplied from the vicinity of the center of the turn table by a nozzle 14, this polishing agent 15 gets between the semiconductor substrate 11 and the polishing pad 13 and therefore polishing proceeds.
The polishing method is about the same at whatever size the semiconductor substrate is. However, sizes of semiconductor substrates become larger for lowering cost of semiconductor devices. In the polishing, rotations of a semiconductor substrate and a turn table are required for maintaining uniformity of polishing within the semiconductor substrate surface. However, enlargement of diameters of semiconductor substrates increases centrifugal force in the peripheral part of a semiconductor substrate by rotation of the semiconductor substrate and a distance from the peripheral part to the center of the semiconductor substrate. Therefore, a phenomenon that it becomes difficult for a polishing agent to get into the central part of the semiconductor substrate is caused. Therefore, uniform polishing is not performed within the semiconductor substrate surface, and as a result, it can cause to degrade the semiconductor substrate flatness. Accordingly, for making the polishing agent get to the central part of the semiconductor substrate so that uniform polishing can be performed within the semiconductor substrate surface, polishing pads on which grooves having various pattern shapes are formed have been invented.
As the groove pattern shapes, there are a lattice shape (see, for example, Japanese Patent Application Laid-open (kokai) No. 2002-100592, No. 2000-286218, No. 2000-354952, and No. 2002-367937), a triangular lattice shape (see, for example, Japanese Patent Application Laid-open (kokai) No. 2000-354952), a tortoiseshell shape, a radial shape (see, for example, Japanese Patent Application Laid-open (kokai) No. 7-321076, No. 2002-100592), a concentric circle shape (see, for example, Japanese Patent Application Laid-open (kokai) No. 2002-100592), a combination of radial pattern grooves and concentric circular or helical grooves (see, for example, Japanese Patent Application Laid-open (kokai) No. 2000-286218, No. 2000-354952, and No. 2002-367937), and so forth. Any one of them has been intended to enhance retention and flowability of a polishing agent and to make the polishing agent get to the central part of a semiconductor substrate, and thereby to uniform polishing amount within the semiconductor substrate surface.
In the case of forming grooves having a lattice, tortoiseshell, or triangular lattice pattern on the polishing pad, there is some cases the grooves become parallel to the diameter direction of the turn table. However, almost all the grooves do not become parallel. If the grooves are parallel to the diameter direction of the turn table, centrifugal force by rotation of the turn table is propagated to the polishing agent as it is. Therefore, the flowability can be held to be large and the polishing agent can get through the grooves to the central part of the semiconductor substrate surface which is closely in contact with the polishing pad. However, if the grooves are not parallel to the diameter direction, the centrifugal force is divided to the groove direction and the direction orthogonal to the grooves and only the force having the groove direction acts on the polishing agent. Therefore, flowability of the polishing agent becomes smaller. Moreover, the polishing agent getting into the grooves immediately below the substrate is divided into flows at branch points of the grooves while going to an outward direction of the turn table. Therefore, an amount of the polishing agent passing through one groove in itself becomes smaller. As the polishing agent getting through the grooves to the central part of the semiconductor substrate surface becomes less, the polishing agent getting between the polishing pad and the semiconductor substrate also becomes less. As a result, a polishing rate at the central part of the semiconductor substrate surface is smaller than a polishing rate in the peripheral part of the semiconductor substrate surface in which the polishing agent is easy to get into between the polishing pad and the semiconductor substrate from parts but grooves. Therefore, there is a case that flatness of a main surface of the semiconductor substrate can be degraded.
On the other hand, in the case of forming concentric circular or helical grooves on the polishing pad, fine concentric circular concavity and convexity, which are called as a polishing ring, are formed on a surface of a semiconductor substrate which is polished with such a polishing pad. They are generated by transcription of concavity and convexity of the polishing pad to be formed by the grooves into a radial region because grooves of the polishing pad are always in contact with the radial region of the surface as viewed from the center of the semiconductor substrate surface. Therefore, in the case of polishing a semiconductor substrate with a polishing pad on which concentric circular or helical grooves are formed, there is a case that surface flatness of the semiconductor substrate can be degraded. Among the polishing pads, there are ones on which radial pattern grooves and concentric circular or helical grooves are combined to be formed on the polishing pad surface. However, as long as the concentric circular or helical grooves exist on the polishing pad, the problem of a polishing ring is inevitably caused and adversely affects the surface flatness of the substrate.
In the case of forming grooves having a radial pattern on the polishing pad, lowering of the flowability of the polishing agent by dispersion of the centrifugal force, flow division of the polishing agent at the groove parts immediately below the substrate, generation of a polishing ring are not caused. Therefore, better polishing can be expected as compared to the above-described groove shapes. In Japanese Patent Application Laid-open (kokai) No. 7-321076, No. 2002-100592, and No. 2000-354952, polishing pads on which such radial pattern grooves are formed has been disclosed.
Among them, in the method for producing a semiconductor device of Japanese Patent Application Laid-open (kokai) No. 7-321076, there has been disclosed a polishing pad whose radial pattern grooves have straight lines or curve to the opposite side to the rotation direction of the polishing pad. In this document, it is supposed to be possible to modify number of the radial pattern grooves to be formed or formation interval of the grooves. However, as the diameter of the substrate becomes larger, 200 mm or more, if groove volumes immediately below the substrate to be polished by the radial pattern grooves are not defined, it becomes difficult for the polishing agent to get to the central part of the substrate main surface being in contact with the polishing pad even if a rotation rate of the polishing turn table or the substrate, load for pressing the substrate, type or concentration of the polishing agent, and so forth, are variously changed. Therefore, there is a possibility that surface flatness of the substrate can be degraded.
Moreover, in Japanese Patent Application Laid-open (kokai) No. 2002-100592, there has been disclosed a polishing pad having radial pattern grooves produced by attaching fan-like pieces of the polishing pad to the polishing turn table surface. However, as with the above-described Japanese Patent Application Laid-open (kokai) No. 7-321076, there is the same problem because groove volumes immediately below the substrate to be polished with the radial pattern grooves are not defined.
Moreover, in Japanese Patent Application Laid-open (kokai) No. 2002-367937, with regard to a polishing pad consisting of non-foaming resin, there has been prescribed widths of upper sides and bottom sides of convex parts to be formed between the grooves formed on the polishing pad, and widths of the groove bottom. Certainly, if grooves to be formed on the polishing pad consisting of non-foaming resin has a lattice shape, a triangular lattice shape, a concentric circle shape, or a helical shape, pitches between the grooves can be constant. Therefore, grooves having prescript sizes can be formed. However, in the case of forming only radial pattern grooves on the polishing pad, if it is attempted to apply the groove sizes prescript in the document to radial pattern grooves, it is not clear whether they may be applied in the most peripheral part of the polishing pad or vicinity of the center of the radial pattern grooves or the whole grooves to be formed may fit into the prescript groove sizes. Therefore, there is a problem in which it is impossible to provide a polishing pad having the most appropriate groove intervals between radial pattern grooves in which the polishing agent can be supplied to the central part of the substrate in the polishing, and there is the same problem as Japanese Patent Application Laid-open (kokai) No. 7-321076 and No. 2002-100592 as described above.
By the way, among the semiconductor substrates as described above, importance of an SOI wafer has been enhanced. This is because an SOI wafer in which a silicon active layer is formed on a silicon oxide film of electrical insulation has an oxide film (hereinafter, referred to as a BOX oxide film) that is an insulator between a supporting wafer and the silicon active layer, and therefore electronic devices to be formed on the silicon active layer have large advantages of high dielectric breakdown strength and lower rate of soft error of α-ray and are devices excellent in high-speed property, low power consumption, high breakdown voltage, environment resistance, and so forth. Moreover, in a thin-film SOI wafer having a silicon active layer with a thickness of 1 μm or less, a PN junction area of source and drain can be reduced in MOS (Metal Oxide Semiconductor)-type semiconductor devices formed on a silicon active layer in the case of being operated with complete depletion type and therefore parasitic capacity is reduced and speeding-up of device-driving can be accomplished. Furthermore, capacity of a BOX oxide film as an insulator layer becomes in series with capacity of the depletion layer to be formed immediately below a gate oxide film and therefore the depletion layer capacity is substantially reduced and lowering of power consumption can be accomplished.
Such an SOI wafer is produced, for example, by forming a BOX oxide film on, at least, one of a first wafer (hereinafter, referred to as a bond wafer) and a second wafer (hereinafter, referred to as a base wafer) each having a main surface in which at least one surface is flattened and mirrored, bonding and joining the two main surfaces of them each other, adding heat treatment to strengthen the joining, then grinding and polishing from the opposite side to the main surface of the bond wafer, and thereby forming a silicon active layer having a predetermined thickness on the insulator film.
Moreover, semiconductor devices are formed on a silicon active layer of an SOI wafer and therefore high film-thickness uniformity is required for the silicon active layer. In particular, in the case that the silicon active layer is 0.3 μm or less, particularly about 0.1 μm, the silicon active layer to be polished in itself is thin. Therefore, stock removal tends to become smaller, and it has become a large problem to remove fine concavity and convexity on the surface of the silicon active layer by touch polishing along with maintaining film-thickness uniformity.
Therefore, a suede-type polishing pad on which grooves having a lattice shape, a triangular lattice shape, a tortoiseshell shape, a radial pattern shape, a concentric circule shape, or a helical shape as described above is formed is also used for polishing of the silicon active layer of an SOI wafer. However, problems in quality in which a polishing ring is generated and good film-thickness uniformity cannot be obtained are caused.